View QU80C186EC25_6457265.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. copyright ? intel corporation, 2004 august, 2004 order number: 272434-006 80c186ec/80c188ec and 80l186ec/80l188ec 16-bit high-integration embedded processors x fully static operation x true cmos inputs and outputs y integrated feature set: e low-power, static, enhanced 8086 cpu core e two independent dma supported uarts, each with an integral baud rate generator e four independent dma channels e 22 multiplexed i/o port pins e two 8259a compatible programmable interrupt controllers e three programmable 16-bit timer/ counters e 32-bit watchdog timer e ten programmable chip selects with integral wait-state generator e memory refresh control unit e power management unit e on-chip oscillator e system level testing support (once mode) y direct addressing capability to 1 mbyte memory and 64 kbyte i/o y low-power operating modes: e idle mode freezes cpu clocks but keeps peripherals active e powerdown mode freezes all internal clocks e powersave mode divides all clocks by programmable prescalar y available in extended temperature range ( b 40 cto a 85 c) y supports 80c187 numerics processor extension (80c186ec only) y package types: e 100-pin eiaj quad flat pack (qfp) e 100-pin plastic quad flat pack (pqfp) e 100-pin shrink quad flat pack (sqfp) y speed versions available (5v): e 25 mhz (80c186ec25/80c188ec25) e 20 mhz (80c186ec20/80c188ec20) e 13 mhz (80c186ec13/80c188ec13) y speed version available (3v): e 16 mhz (80l186ec16/80l188ec16) e 13 mhz (80l186ec13/80l188ec13) the 80c186ec is a member of the 186 integrated processor family. the 186 integrated processor family incorporates several different vlsi devices all of which share a common cpu architecture: the 8086/8088. the 80c186ec uses the latest high density chmos technology to integrate several of the most common system peripherals with an enhanced 8086 cpu core to create a powerful system on a single monolithic silicon die.
80c186ec/80c188ec and 80l186ec/80l188ec 16-bit high-integration embedded processor contents page introduction 4 80c186ec core architecture 4 bus interface unit 4 clock generator 4 80c186ec peripheral architecture 5 programmable interrupt controllers 7 timer/counter unit 7 serial communications unit 7 dma unit 7 chip-select unit 7 i/o port unit 7 refresh control unit 7 watchdog timer unit 7 power management unit 8 80c187 interface (80c186ec only) 8 once test mode 8 package information 8 prefix identification 8 pin descriptions 8 pinout 15 package thermal specifications 24 electrical specifications 25 absolute maximum ratings 25 contents page recommended connections 25 dc specifications 26 i cc versus frequency and voltage 29 pdtmr pin delay calculation 29 ac specifications 30 ac characteristicse80c186ec25 30 ac characteristicse80c186ec20/13 32 ac characteristicse80l186ec13 33 ac characteristicse80l186ec16 34 relative timings 35 serial port mode 0 timings 36 ac test conditions 37 ac timing waveforms 37 derating curves 40 reset 40 bus cycle waveforms 43 execution timings 50 instruction set summary 51 errata 57 revision history 57 2
80c186ec/188ec, 80l186ec/188ec 272434 1 note: pin names in parentheses apply to the 80c188ec/80l188ec figure 1. 80c186ec/80l186ec block diagram 3
80c186ec/188ec, 80l186ec/188ec introduction unless specifically noted, all references to the 80c186ec apply to the 80c188ec, 80l186ec, and 80l188ec. references to pins that differ between the 80c186ec/80l186ec and the 80c188ec/ 80l188ec are given in parentheses. the ``l'' in the part number denotes low voltage operation. physi- cally and functionally, the ``c'' and ``l'' devices are identical. the 80c186ec is one of the highest integration members of the 186 integrated processor family. two serial ports are provided for services such as interprocessor communication, diagnostics and mo- dem interfacing. four dma channels allow for high speed data movement as well as support of the on- board serial ports. a flexible chip select unit simpli- fies memory and peripheral interfacing. the three general purpose timer/counters can be used for a variety of time measurement and waveform genera- tion tasks. a watchdog timer is provided to insure system integrity even in the most hostile of environ- ments. two 8259a compatible interrupt controllers handle internal interrupts, and, up to 57 external in- terrupt requests. a dram refresh unit and 24 multi- plexed i/o ports round out the feature set of the 80c186ec. the future set of the 80c186ec meets the needs of low-power, space-critical applications. low-power applications benefit from the static design of the cpu and the integrated peripherals as well as low voltage operation. minimum current consumption is achieved by providing a powerdown mode that halts operaton of the device and freezes the clock cir- cuits. peripheral design enhancements ensure that non-initialized peripherals consume little current. the 80l186ec is the 3v version of the 80c186ec. the 80l186ec is functionally identical to the 80c186ec embedded processor. current 80c186ec users can easily upgrade their designs to use the 80l186ec and benefit from the reduced power consumption inherent in 3v operation. figure 1 shows a block diagram of the 80c186ec/ 80c188ec. the execution unit (eu) is an enhanced 8086 cpu core that includes: dedicated hardware to speed up effective address calculations, enhanced execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions and fully static oper- ation. the bus interface unit (biu) is the same as that found on the original 186 family products, ex- cept the queue-status mode has been deleted and buffer interface control has been changed to ease system design timings. an independent internal bus is used for communication between the biu and on- chip peripherals. 80c186ec core architecture bus interface unit the 80c186ec core incorporates a bus controller that generates local bus control signals. in addition, it employs a hold/hlda protocol to share the local bus with other bus masters. the bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) in- formation. it is also responsible for reading data from the local bus during a read operation. a ready input pin is provided to extend a bus cycle beyond the minimum four states (clocks). the bus controller also generates two control sig- nals (den and dt/r ) when interfacing to external transceiver chips. this capability allows the addition of transceivers for simple buffering of the multi- plexed address/data bus. clock generator the 80c186ec provides an on-chip clock generator for both internal and external clock generation. the clock generator features a crystal oscillator, a divide- by-two counter and three low-power operating modes. the oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. alternatively, the oscilla- tor circuit may be driven from an external clock source. figure 2 shows the various operating modes of the oscillator circuit. the crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. this counter is used to drive all internal phase clocks and the exter- nal clkout signal. clkout is a 50% duty cycle processor clock and can be used to drive other sys- tem components. all ac timings are referenced to clkout. the following parameters are recommended when choosing a crystal: temperature range: application specific esr (equivalent series res.): 40 x max c0 (shunt capacitance of crystal): 7.0 pf max c l (load capacitance): 20 pf g 2pf drive level: 1 mw (max) 4
80c186ec/188ec, 80l186ec/188ec 272434 2 note: 1. the lc network is only required when using a third overtone crystal. figure 2. 80c186ec clock connections 80c186ec peripheral architecture the 80c186ec integrates several common system peripherals with a cpu core to create a compact, yet powerful system. the integrated peripherals are de- signed to be flexbile and provide logical interconnec- tions between supporting units (e.g., the dma unit can accept requests from the serial communica- tions unit). the list of integrated peripherals includes: e two cascaded, 8259a compatible, programma- ble interrupt controllers e 3-channel timer/counter unit e 2-channel serial communications unit e 4-channel dma unit e 10-output chip-select unit e 32-bit watchdog timer unit e i/o port unit e refresh control unit e power management unit the registers associated with each integrated pe- ripheral are contained within a 128 x 16-bit register file called the peripheral control block (pcb). the base address of the pcb is programmable and can be located on any 256 byte address boundary in ei- ther memory or i/o space. figure 3 provides a list of the registers associated with the pcb. the register bit summary individually lists all of the registers and identifies each of their programming attributes. 5
80c186ec/188ec, 80l186ec/188ec pcb function offset 00h master pic port 0 02h master pic port 1 04h slave pic port 0 06h slave pic port 1 08h reserved 0ah scu int. req. ltch. 0ch dma int. req. ltch. 0eh tcu int. req. ltch. 10h reserved 12h reserved 14h reserved 16h reserved 18h reserved 1ah reserved 1ch reserved 1eh reserved 20h wdt reload high 22h wdt reload low 24h wdt count high 26h wdt count low 28h wdt clear 2ah wdt disable 2ch reserved 2eh reserved 30h t0 count 32h t0 compare a 34h t0 compare b 46h t0 control 38h t1 count 3ah t1 compare a 3ch t1 compare b 3eh t1 control pcb function offset 40h t2 count 42h t2 compare 44h reserved 46h t2 control 48h port 3 direction 4ah port 3 pin state 4ch port 3 mux control 4eh port 3 data latch 50h port 1 direction 52h port 1 pin state 54h port 1 mux control 56h port 1 data latch 58h port 2 direction 5ah port 2 pin state 5ch port 2 mux control 5eh port 2 data latch 60h scu 0 baud 62h scu 0 count 64h scu 0 control 66h scu 0 status 68h scu 0 rbuf 6ah scu 0 tbuf 6ch reserved 6eh reserved 70h scu 1 baud 72h scu 1 count 74h scu 1 control 76h scu 1 status 78h scu 1 rbuf 7ah scu 1 tbuf 7ch reserved 7eh reserved pcb function offset 80h gcs0 start 82h gcs0 stop 84h gcs1 start 86h gcs1 stop 88h gcs2 start 8ah gcs2 stop 8ch gcs3 start 8eh gcs3 stop 90h gcs4 start 92h gcs4 stop 94h gcs5 start 96h gcs5 stop 98h gcs6 start 9ah gcs6 stop 9ch gcs7 start 9eh gcs7 stop a0h lcs start a2h lcs stop a4h ucs start a6h ucs stop a8h relocation register aah reserved ach reserved aeh reserved b0h refresh base addr. b2h refresh time b4h refresh control b6h refresh address b8h power control bah reserved bch step id beh powersave pcb function offset c0h dma 0 source low c2h dma 0 source high c4h dma 0 dest. low c6h dma 0 dest. high c8h dma 0 count cah dma 0 control cch dma module pri. ceh dma halt d0h dma 1 source low d2h dma 1 source high d4h dma 1 dest. low d6h dma 1 dest. high d8h dma 1 count dah dma 1 control dch reserved deh reserved e0h dma 2 source low e2h dma 2 source high e4h dma 2 dest. low e6h dma 2 dest. high e8h dma 2 count eah dma 2 control ech reserved eeh reserved f0h dma 3 source low f2h dma 3 source high f4h dma 3 dest. low f6h dma 3 dest. high f8h dma 3 count fah dma 3 control fch reserved feh reserved figure 3. peripheral control block registers 6
80c186ec/188ec, 80l186ec/188ec programmable interrupt controllers the 80c186ec utilizes two 8259a compatible pro- grammable interrupt controllers (pic) to manage both internal and external interrupts. the 8259a modules are configured in a master/slave arrange- ment. seven of the external interrupt pins, int0 through int6, are connected to the master 8259a module. the eighth external interrupt pin, int7, is connected to the slave 8259a module. there are a total of 11 internal interrupt sources from the integrated peripherals: 4 serial, 4 dma and 3 timer/counter. timer/counter unit the 80c186ec timer/counter unit (tcu) provides three 16-bit programmable timers. two of these are highly flexible and are connected to external pins for external control or clocking. the third timer is not connected to any external pins and can only be clocked internally. however, it can be used to clock the other two timer channels. the tcu can be used to count external events, time external events, gen- erate non-repetitive waveforms or generate timed in- terrupts. serial communications unit the 80c186ec serial communications unit (scu) contains two independent channels. each channel is identical in operation except that only channel 0 is directly supported by the integrated interrupt control- ler (the channel 1 interrupts are routed to external interrupt pins). each channel has its own baud rate generator and can be internally or externally clocked up to one half the processor operating frequency. both serial channels can request service from the dma unit thus providing block reception and trans- mission without cpu intervention. independent baud rate generators are provided for each of the serial channels. for the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit shifting register logic. a 1x baud clock is provided in the synchronous mode. dma unit the four channel direct memory access (dma) unit is comprised of two modules with two channels each. all four channels are identical in operation. dma transfers can take place from memory to mem- ory, i/o to memory, memory to i/o or i/o to i/o. dma requests can be external (on the drq pins), internal (from timer 2 or a serial channel) or soft- ware initiated. the dma unit transfers data as bytes only. each data transfer requires at least two bus cycles, one to fetch data and one to deposit. the minimum clock count for each transfer is 8, but this will vary depend- ing on synchronization and wait states. chip-select unit the 80c186ec chip-select unit (csu) integrates logic which provides up to ten programmable chip- selects to access both memories and peripherals. in addition, each chip-select can be programmed to automatically insert additional clocks (wait states) into the current bus cycle, and/or automatically ter- minate a bus cycle independent of the condition of the ready input pin. i/o port unit the i/o port unit on the 80c186ec supports two 8-bit channels and one 6-bit channel of input, output or input/output operation. port 1 is multiplexed with the chip select pins and is output only. port 2 is mul- tiplexed with the pins for serial channels 1 and 2. all port 2 pins are input/output. port 3 has a total of 6 pins: four that are multiplexed with dma and serial port interrupts and two that are non-multiplexed, open drain i/o. refresh control unit the refresh control unit (rcu) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. a 9-bit counter controls the number of clocks between re- fresh requests. a 12-bit address generator is maintained by the rcu and is presented on the a12:1 address lines during the refresh bus cycle. address bits a19:13 are pro- grammable to allow the refresh address block to be located on any 8 kbyte boundary. watchdog timer unit the watchdog timer unit (wdt) allows for graceful recovery from unexpected hardware and software upsets. the wdt consists of a 32-bit counter that decrements every clock cycle. if the counter reach- es zero before being reset, the wdtout pin is 7
80c186ec/188ec , 80l186ec/188ec pulle d lo w fo r fou r cloc k cycles . logicall y anding th e wdtout pi n wit h th e power-o n rese t signa l al- low s th e wd t t o rese t th e devic e i n th e even t o f a wd t timeout . i f a les s drasti c metho d o f recover y is desired . wdtout ca n b e connecte d directl y t o nmi o r on e o f th e in t inpu t pins . th e wd t ma y als o be use d a s a genera l purpos e timer. powe r managemen t unit th e 80c186e c powe r managemen t uni t (pmu ) is provide d t o contro l th e powe r consumptio n o f the device . th e pm u provide s fou r powe r management modes : active , powersave , idl e an d powerdown. activ e mod e indicate s tha t al l unit s o n the 80c186e c ar e operatin g at ? th e clki n frequency. idl e mod e freeze s th e clock s o f th e executio n and bu s unit s a t a logi c zer o stat e (al l peripheral s contin- u e t o operat e normally). th e powerdow n mod e freeze s al l interna l clock s at a logi c zer o leve l an d disable s th e crysta l oscillator. i n powersav e mode , al l interna l cloc k signal s ar e di- vide d b y a programmabl e prescala r (u p to 1/64 the norma l frequency) . powersav e mod e ca n b e used wit h idl e mod e a s wel l a s durin g norma l (active mode ) operation. 80c18 7 interfac e (80c186e c only) th e 80c186e c support s th e direc t connectio n of th e 80c18 7 numeric s processo r extension . the 80c18 7 ca n dramaticall y improv e th e performance o f calculatio n intensiv e applications. onc e tes t mode t o facilitat e testin g an d inspectio n o f device s when fixe d int o a targe t system , th e 80c186e c ha s a test mod e availabl e whic h force s al l outpu t an d input/ outpu t pin s t o b e place d i n th e high-impedance state . onc e stand s fo r o n circui t emulation, th e onc e mod e i s selecte d b y forcin g the a19/s6/once pi n lo w durin g a processo r reset (thi s pi n i s weakl y hel d hig h durin g rese t t o prevent inadvertan t entranc e int o onc e mode). packag e information thi s sectio n describe s th e pi n functions , pinou t and therma l characteristic s fo r th e 80c186e c i n the plasti c qua d fla t pac k (jede c pqfp) , th e eiaj qua d fla t pac k (qfp ) an d th e shrin k qua d flat pac k (sqfp) . fo r complet e packag e specifications an d information , se e th e inte l packagin g outlines an d dimension s guid e (orde r number : 231369). prefi x identification tabl e 1 list s th e prefi x identifications. tabl e 1 : prefi x identification prefi x note packag e temperature typ e range qf p (eiaj ) extended 1 pqf p extended/commercial 1 sqf p extended/commercial 1 qf p (eiaj ) commercial note: 1 . th e 5 v 2 5 mh z versio n i s onl y availabl e i n commercial temperatur e rang e correspondin g t o 0 ? c to a 70 c am- bient. pi n descriptions eac h pi n o r logica l se t o f pin s i s describe d i n table 2 , ther e ar e fou r column s fo r eac h entr y i n th e pin descriptio n table . th e followin g section s describe eac h column. colum n 1 . pi n name i n thi s colum n i s a mnemoni c tha t de- scribe s th e pi n function . negatio n o f the signa l nam e (i.e . resin ) implie s tha t the signa l i s activ e low. colum n 2 . pi n type a pi n ma y b e eithe r powe r (p) , ground (g) , inpu t onl y (i) , outpu t onl y (o ) o r in- put/outpu t (i/o) . pleas e not e tha t some pin s hav e mor e tha n 1 function. a19/s6/once , fo r example , i s normally a n outpu t bu t function s a s a n inpu t dur- in g reset . fo r thi s reason a19/s6/once i s classifie d a s a n input/ outpu t pin. colum n 3 . inpu t typ e (fo r i an d i/ o type s only) ther e ar e tw o differen t type s o f input pin s o n th e 80c186ec : asynchronous an d synchronous. asynchronous pins requir e tha t setu p an d hol d time s b e met onl y to guarante e recognition . synchro- nous inpu t pin s requir e tha t th e setup an d hol d time s b e me t to guarantee prope r operation . state d simply , missing a setu p o r hol d o n a n asynchronou s pin wil l resul t i n somethin g mino r (i.e . a timer coun t wil l b e missed ) wherea s missin g a setu p o r hol d o n a synchronou s pi n will resul t i n syste m failur e (th e syste m will loc k up). a n inpu t pi n ma y als o b e edg e o r level sensitive. 8 x x x x 1 . to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
80c186ec/188ec, 80l186ec/188ec column 4: output states (for o and i/o types only) the state of an output or i/o pin is de- pendent on the operating mode of the device. there are four modes of opera- tion that are different from normal active mode: bus hold, reset, idle mode, pow- erdown mode. this column describes the output pin state in each of these modes. the legend for interpreting the information in the pin descriptions is shown in table 1. as an example, please refer to the table entry for ad12:0. the ``i/o'' signifies that the pins are bidirec- tional (i.e. have both an input and output function). the ``s'' indicates that, as an input the signal must be synchronized to clkout for proper operation. the ``h(z)'' indicates that these pins will float while the processor is in the hold acknowledge state. r(z) indicates that these pins will float while resin is low. p(0) and i(0) indicate that these pins will drive 0 when the device is in either powerdown or idle mode. some pins, the i/o ports for example, can be pro- grammed to perform more than one function. multi- function pins have a ``/'' in their signal name be- tween the different functions (i.e. p3.0/rxi1). if the input pin type or output pin state differ between func- tions, then that will be indicated by separating the state (or type) with a ``/'' (i.e. h(x)/h(q)). in this example when the pin is configured as p3.0 then its hold output state is h(x); when configured as rxi1 its output state is h(q). all pins float while the processor is in the once mode (with the exception of oscout). table 1. pin description nomenclature symbol description p power pin (apply a v cc voltage) g ground (connect to v ss ) i input only pin o output only pin i/o input/output pin s(e) synchronous, edge sensitive s(l) synchronous, level sensitive a(e) asynchronous, edge sensitive a(l) asynchronous, level sensitive h(1) output driven to v cc during bus hold h(0) output driven to v ss during bus hold h(z) output floats during bus hold h(q) output remains active during bus hold h(x) output retains current state during bus hold r(wh) output weakly held at v cc during reset r(1) output driven to v cc during reset r(0) output driven to v ss during reset r(z) output floats during reset r(q) output remains active during reset r(x) output retains current state during reset i(1) output driven to v cc during idle mode i(0) output driven to v ss during idle mode i(z) output floats during idle mode i(q) output remains active during idle mode i(x) output retains current state during idle mode p(1) output driven to v cc during powerdown mode p(0) output driven to v ss during powerdown mode p(z) output floats during powerdown mode p(q) output remains active during powerdown mode p(x) output retains current state during powerdown mode 9
80c186ec/188ec, 80l186ec/188ec table 2. pin descriptions pin name pin input output pin description type type states v cc pe e power a 5v g 10% power supply connection v ss ge e ground clkin i a(e) e clock input is the external clock input. an external oscillator operating at two times the required processor operating frequency can be connected to clkin. for crystal operation, clkin (along with oscout) are the crystal connections to an internal pierce oscillator. oscout o e h(q) oscillator output is only used when using a crystal to generate the internal clock. oscout (along with clkin) r(q) are the crystal connections to an internal pierce oscillator. i(q) this pin can not be used as 2x clock output for non- p(x) crystal applications (i.e. this pin is not connected for non- crystal applications). clkout o e h(q) clock output provides a timing reference for inputs and outputs of the processor, and is one-half the input clock r(q) (clkin) frequency. clkout has a 50% duty cycle and i(q) transitions every falling edge of clkin. p(x) resin i a(l) e reset in causes the processor to immediately terminate any bus cycle in progress and assume an initialized state. all pins will be driven to a known state, and resout will also be driven active. the rising edge (low-to-high) transition synchronizes clkout with clkin before the processor begins fetching opcodes at memory location 0ffff0h. resout o e h(0) reset output that indicates the processor is currently in the reset state. resout will remain active as long as r(1) resin remains active. i(0) p(0) pdtmr i/o a(l) h(wh) power-down timer pin (normally connected to an external capacitor) that determines the amount of time the r(z) processors waits after an exit from powerdown before p(wh) resuming normal operation. the duration of time required i(wh) will depend on the startup characteristics of the crystal oscillator. nmi i a(e) e non-maskable interrupt input causes a type-2 interrupt to be serviced by the cpu. nmi is latched internally. test /busy i a(e) e test is used during the execution of the wait instruction to suspend cpu operation until the pin is sampled active (test) (low). test is alternately known as busy when interfacing with an 80c187 numerics coprocessor (80c186ec only). a19/s6/once i/o a(l) h(z) this pin drives address bit 19 during the address phase of the bus cycle. during t2 and t3 this pin functions as r(wh) status bit 6. s6 is low to indicate cpu bus cycles and high i(0) to indicate dma or refresh bus cycles. during a processor p(0) reset (resin active) this pin becomes the once input pin. holding this pin low during reset will force the part into once mode. note: pin names in parentheses apply to the 80c188ec/80l188ec. 10
80c186ec/188ec, 80l186ec/188ec table 2. pin descriptions (continued) pin name pin input output pin description type type states a18/s5 i/o a(l) h(z) these pins drive address information during the address phase of the bus cycle. during t2 and t3 these pins drive a17/s4 r(wh) status information (which is always 0 on the 80c186ec). a16/s3 i(0) these pins are used as inputs during factory test; driving (a15:8) p(0) these pins low during reset will cause unspecified operation. on the 80c188ec, a15:8 provide valid address information for the entire bus cycle. ad15/cas2 i/o s(l) h(z) these pins are part of the multiplexed address and data bus. during the address phase of the bus cycle, address bits ad14/cas1 r(z) 15 through 13 are presented on these pins and can be ad13/cas0 i(0) latched using ale. data information is transferred during the p(0) data phase of the bus cycle. pins ad15:13/cas2:0 drive the 82c59 slave address information during interrupt acknowledge cycles. ad12:0 i/o s(l) h(z) these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0 (ad7:0) r(z) through 12 (0 through 7 on the 80c188ec) are presented on i(0) the bus and can be latched using ale. data information is p(0) transferred during the data phase of the bus cycle. s2:0 o e h(z) bus cycle status are encoded on these pins to provide bus transaction information. s2:0 are encoded as follows: r(1) i(1) p(1) s2 s1 s0 bus cycle initiated 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 instruction queue fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 passive (no bus activity) ale o e h(0) address latch enable output is used to strobe address information into a transparent type latch during the address r(0) phase of the bus cycle. i(0) p(0) bhe o e h(z) byte high enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data (rfsh ) r(z) bus. bhe and a0 have the following logical encoding: i(1) p(1) a0 bhe encoding (for 80c186ec/ 80l186ec only) 0 0 word transfer 0 1 even byte transfer 1 0 odd byte transfer 1 1 refresh operation on the 80c188ec/80l188ec, rfsh is asserted low to indicate a refresh bus cycle. note: pin names in parentheses apply to the 80c188ec/80l188ec. 11
80c186ec/188ec, 80l186ec/188ec table 2. pin descriptions (continued) pin name pin input output pin description type type states rd o e h(z) read output signals that the accessed memory or i/o device should drive data information onto the data bus. r(z) i(1) p(1) wr o e h(z) write output signals that data available on the data bus are to be written into the accessed memory or i/o device. r(z) i(1) p(1) ready i a(l) e ready input to signal the completion of a bus cycle. ready must be active to terminate any 80c186ec bus cycle, unless s(l) it is ignored by correctly programming the chip-select unit. (note 1) den o e h(z) data enable output to control the enable of bi-directional transceivers in a buffered system. den is active only when r(z) data is to be transferred on the bus. i(1) p(1) dt/r o e h(z) data transmit/receive output controls the direction of a bi- directional buffer in a buffered system. r(z) i(x) p(x) lock i/o a(l) h(z) lock output indicates that the bus cycle in progress is not interruptable. the processor will not service other bus r(z) requests (such as hold) while lock is active. this pin is i(x) configured as a weakly held high input while resin is active p(x) and must not be driven low. hold i a(l) e hold request input to signal that an external bus master wishes to gain control of the local bus. the processor will relinquish control of the local bus between instruction boundaries that are not locked. hlda o e h(1) hold acknowledge output to indicate that the processor has relinquished control of the local bus. when hlda is r(0) asserted, the processor will (or has) floated its data bus and i(0) control signals allowing another bus master to drive the p(0) signals directly. ncs o e h(1) numerics coprocessor select output is generated when acessing a numerics coprocessor. this signal does not exist r(1) on the 80c188ec/80l188ec. i(1) p(1) error i a(l) e error input that indicates the last numerics processor extension operation resulted in an exception condition. an interrupt type 16 is generated if error is sampled active at the beginning of a numerics operation. systems not using an 80c187 must tie error to v cc . this signal does not exist on the 80c188ec/80l188ec. note: pin names in parentheses apply to the 80c188ec/80l188ec. 12
80c186ec/188ec, 80l186ec/188ec table 2. pin descriptions (continued) pin name pin input output pin description type type states pereq i a(l) e processor extension request signals that a data transfer between an 80c187 numerics processor extension and memory is pending. systems not using an 80c187 must tie this pin to v ss . this signal does not exist on the 80c188ec/80l188ec. ucs o e h(1) upper chip select will go active whenever the address of a memory or i/o bus cycle is within the address range r(1) programmed by the user. after reset, ucs is configured to i(1) be active for memory accesses between 0ffc00h and p(1) 0fffffh. lcs o e h(1) lower chip select will go active whenever the address of a memory or i/o bus cycle is within the address range r(1) programmed by the user. lcs is inactive after a reset. i(1) p(1) p1.0/gcs0 o e h(x)/h(1) these pins provide a multiplexed function. if enabled, each pin can provide a general purpose chip select p1.1/gcs1 r(1) output which will go active whenever the address of a p1.2/gcs2 i(x)/i(1) memory or i/o bus cycle is within the address limitations p1.3/gcs3 p(x)/p(1) programmed by the user. when not programmed as a p1.4/gcs4 chip-select, each pin may be used as a general purpose p1.5/gcs5 output port. p1.6/gcs6 p1.7/gcs7 t0out o e h(q) timer output pins can be programmed to provide single clock or continuous waveform generation, depending on t1out r(1) the timer mode selected. i(q) p(x) t0in i a(l) e timer input is used either as clock or control signals, depending on the timer mode selected. this pin may be t1in a(e) either level or edge sensitive depending on the programming mode. int7:0 i a(l) e maskable interrupt input will cause a vector to a specific type interrupt routine. the int6:0 pins can be used as a(e) cascade inputs from slave 8259a devices. the int pins can be configured as level or edge sensitive. inta o e h(1) interrupt acknowledge output is a handshaking signal used by external 82c59a programmable interrupt r(1) controllers. i(1) p(1) p3.5 i/o a(l) h(x) bidirectional, open-drain port pins. p3.4 r(z) i(x) h(x) p3.3/dmai1 o e h(x) dma interrupt output goes active to indicate that the channel has completed a transfer. dmai1 and dmai0 are p3.2/dmai0 r(0) multiplexed with output only port functions. i(q) p(x) note: pin names in parentheses apply to the 80c188ec/80l188ec. 13
80c186ec/188ec, 80l186ec/188ec table 2. pin descriptions (continued) pin name pin input output pin description type type states p3.1/txi1 o e h(x)/h(q) transmit interrupt output goes active to indicate that serial channel 1 has completed a transfer. txi1 is r(0) multiplexed with an output only port function. i(q) p(x) p3.0/rxi1 o e h(x)/h(q) receive interrupt output goes active to indicate that serial channel 1 has completed a reception. rxi1 is r(0) multiplexed with an output only port function. i(q) p(x) wdtout o e h(q) watchdog timer output is driven low for four clock cycles when the watchdog timer reaches zero. wdtout r(1) may be anded with the power-on reset signal to reset the i(q) processor when the watchdog timer is not properly reset. p(x) p2.7/cts1 i/o a(l) h(x) clear-to-send input is used to prevent the transmission of serial data on the txd signal pin. cts1 and cts0 are p2.3/cts0 r(z) multiplexed with an i/o port function. i(x) p(x) p2.6/bclk1 i/o a(l)/ h(x) baud clock input can be used as an alternate clock source for each of the integrated serial channels. the p2.2/bclk0 a(e) r(z) bclk inputs are multiplexed with i/o port functions. the i(x) bclk input frequency cannot exceed (/2 the operating p(x) frequency of the processor . p2.5/txd1 i/o a(l) h(q) transmit data output provides serial data information. the txd outputs are multiplexed with i/o port functions. p2.1/txd0 r(z) during synchronous serial communications, txd will i(x)/i(q) function as a clock output. p(x) p2.4/rxd1 i/o a(l) h(x)/h(q) receive data input accepts serial data information. the rxd pins are multiplexed with i/o port functions. during p2.0/rxd0 r(z) synchronous serial communications, rxd is bi-directional i(x)/i(q) and will become an output for transmission of data (txd p(x) becomes the clock). drq3:0 i a(l) e dma request input pins are used to request a dma transfer. the timing of the request is dependent on the programmed synchronization mode. notes: 1. ready is a(e) for the rising edge of clkout, s(e) for the falling edge of clkout. 2. pin names in parentheses apply to the 80c188ec/80l188ec. 14
80c186ec/188ec, 80l186ec/188ec pinout tables 3 and 4 list the pin names with package loca- tion for the 100-pin plastic quad flat pack (pqfp) component. figure 4 depicts the pqfp package as viewed from the top side of the component (i.e. con- tacts facing down). tables 5 and 6 list the pin names with package loca- tion for the 100-pin eiaj quad flat pack (qfp) com- ponent. figure 5 depicts the qfp package as viewed from the top side of the component (i.e. contacts facing down). tables 7 and 8 list the pin names with package loca- tion for the 100-pin shrink quad flat pack (sqfp) component. figure 6 depicts the sqfp package as viewed from the top side of the component (i.e., con- tacts facing down). table 3. pqfp pin functions with location ad bus name pin ad0 73 ad1 72 ad2 71 ad3 70 ad4 66 ad5 65 ad6 64 ad7 63 ad8 (a8) 60 ad9 (a9) 59 ad10 (a10) 58 ad11 (a11) 57 ad12 (a12) 56 ad13/cas0 55 (a13/cas0) ad14/cas1 54 (a14/cas1) ad15/cas2 53 (a15/cas2) a16/s3 77 a17/s4 76 a18/s5 75 a19/s6/once 74 bus control name pin ale 52 bhe (rfsh )51 s0 78 s1 79 s2 80 rd 50 wr 49 ready 85 den 47 dt/r 46 lock 48 hold 44 hlda 45 inta 34 power and ground name pin v cc 13 v cc 14 v cc 38 v cc 62 v cc 67 v cc 69 v cc 86 v ss 12 v ss 15 v ss 37 v ss 39 v ss 61 v ss 68 v ss 87 processor control name pin resin 8 resout 7 clkin 10 oscout 11 clkout 6 test /busy 83 (test ) pereq (v ss )81 ncs (n.c.) 35 error (v cc )84 pdtmr 9 nmi 82 int0 30 int1 31 int2 32 int3 33 int4 40 int5 41 int6 42 int7 43 i/o name pin ucs 88 lcs 89 p1.7/gcs7 90 p1.6/gcs6 91 p1.5/gcs5 92 p1.4/gcs4 93 p1.3/gcs3 94 p1.2/gcs2 95 p1.1/gcs1 96 p1.0/gcs0 97 p2.7/cts1 23 p2.6/bclk1 22 p2.5/txd1 21 p2.4/rxd1 20 p2.3/cts0 19 p2.2/bclk0 18 p2.1/txd0 17 p2.0/rxd0 16 p3.5 29 p3.4 28 p3.3/dmai1 27 p3.2/dmai0 26 p3.1/txi1 25 p3.0/rxi1 24 t0in 3 t0out 2 t1in 5 t1out 4 drq0 98 drq1 99 drq2 100 drq3 1 wdtout 36 15
80c186ec/188ec, 80l186ec/188ec table 4. pqfp pin locations with pin name pin name 1 drq3 2 t0out 3 t0in 4 t1out 5 t1in 6 clkout 7 resout 8 resin 9 pdtmr 10 clkin 11 oscout 12 v ss 13 v cc 14 v cc 15 v ss 16 p2.0/rxd0 17 p2.1/txd0 18 p2.2/bclk0 19 p2.3/cts0 20 p2.4/rxd1 21 p2.5/txd1 22 p2.6/bclk1 23 p2.7/cts1 24 p3.0/rxi1 25 p3.1/txi1 pin name 26 dmai0/p3.2 27 dmai1/p3.3 28 p3.4 29 p3.5 30 int0 31 int1 32 int2 33 int3 34 inta 35 ncs (n.c.) 36 wdtout 37 v ss 38 v cc 39 v ss 40 int4 41 int5 42 int6 43 int7 44 hold 45 hlda 46 dt/r 47 den 48 lock 49 wr 50 rd pin name 51 bhe (rfsh ) 52 ale 53 ad15 (a15) 54 ad14 (a14) 55 ad13 (a13) 56 ad12 (a12) 57 ad11 (a11) 58 ad10 (a10) 59 ad9 (a9) 60 ad8 (a8) 61 v ss 62 v cc 63 ad7 64 ad6 65 ad5 66 ad4 67 v cc 68 v ss 69 v cc 70 ad3 71 ad2 72 ad1 73 ad0 74 a19/s6/once 75 a18/s5 pin name 76 a17/s4 77 a16/s3 78 s0 79 s1 80 s2 81 pereq (v ss ) 82 nmi 83 test 84 error (v cc ) 85 ready 86 v cc 87 v ss 88 ucs 89 lcs 90 p1.7/gcs7 91 p1.6/gcs6 92 p1.5/gcs5 93 p1.4/gcs4 94 p1.3/gcs3 95 p1.2/gcs2 96 p1.1/gcs1 97 p1.0/gcs0 98 drq0 99 drq1 100 drq2 16
80c186ec/188ec , 80l186ec/188ec 27243 4 C 3 note: thi s i s th e fp o numbe r locatio n (indicate d b y xs). figur e 4 . 100-pi n plasti c qua d fla t pac k packag e (pqfp) 17 x
80c186ec/188ec, 80l186ec/188ec table 5. qfp pin names with package location ad bus name pin ad0 76 ad1 75 ad2 74 ad3 73 ad4 69 ad5 68 ad6 67 ad7 66 ad8 (a8) 63 ad9 (a9) 62 ad10 (a10) 61 ad11 (a11) 60 ad12 (a12) 59 ad13/cas0 58 (a13/cas0) ad14/cas1 57 (a14/cas1) ad15/cas2 56 (a15/cas2) a16/s3 80 a17/s4 79 a18/s5 78 a19/s6/once 77 bus control name pin ale 55 bhe (rfsh )54 s0 81 s1 82 s2 83 rd 53 wr 52 ready 88 den 50 dt/r 49 lock 51 hold 47 hlda 48 inta 37 power and ground name pin v cc 16 v cc 17 v cc 41 v cc 65 v cc 70 v cc 72 v cc 89 v ss 15 v ss 18 v ss 40 v ss 42 v ss 64 v ss 71 v ss 90 processor control name pin resin 11 resout 10 clkin 13 oscout 14 clkout 9 test /busy 86 (test ) pereq (v ss )84 ncs (n.c.) 38 error (v cc )87 pdtmr 12 nmi 85 int0 33 int1 34 int2 35 int3 36 int4 43 int5 44 int6 45 int7 46 i/o name pin ucs 91 lcs 92 p1.7/gcs7 93 p1.6/gcs6 94 p1.5/gcs5 95 p1.4/gcs4 96 p1.3/gcs3 97 p1.2/gcs2 98 p1.1/gcs1 99 p1.0/gcs0 100 p2.7/cts1 26 p2.6/bclk1 25 p2.5/txd1 24 p2.4/rxd1 23 p2.3/cts0 22 p2.2/bclk0 21 p2.1/txd0 20 p2.0/rxd0 19 p3.5 32 p3.4 31 p3.3/dmai1 30 p3.2/dmai0 29 p3.1/txi1 28 p3.0/rxi1 27 t0in 6 t0out 5 t1in 8 t1out 7 drq0 1 drq1 2 drq2 3 drq3 4 wdtout 39 18
80c186ec/188ec, 80l186ec/188ec table 6. qfp package location with pin names pin name 1 drq0 2 drq1 3 drq2 4 drq3 5 t0out 6 t0in 7 t1out 8 t1in 9 clkout 10 resout 11 resin 12 pdtmr 13 clkin 14 oscout 15 v ss 16 v cc 17 v cc 18 v ss 19 p2.0/rxd0 20 p2.1/txd0 21 p2.2/bclk0 22 p2.3/cts0 23 p2.4/rxd1 24 p2.5/txd1 25 p2.6/bclk1 pin name 26 p2.7/cts1 27 p3.0/rxi1 28 p3.1/txi1 29 dmai0/p3.2 30 dmai1/p3.3 31 p3.4 32 p3.5 33 int0 34 int1 35 int2 36 int3 37 inta 38 ncs (n.c.) 39 wdtout 40 v ss 41 v cc 42 v ss 43 int4 44 int5 45 int6 46 int7 47 hold 48 hlda 49 dt/r 50 den pin name 51 lock 52 wr 53 rd 54 bhe (rfsh ) 55 ale 56 ad15 (a15) 57 ad14 (a14) 58 ad13 (a13) 59 ad12 (a12) 60 ad11 (a11) 61 ad10 (a10) 62 ad9 (a9) 63 ad8 (a8) 64 v ss 65 v cc 66 ad7 67 ad6 68 ad5 69 ad4 70 v cc 71 v ss 72 v cc 73 ad3 74 ad2 75 ad1 pin name 76 ad0 77 a19/s6/once 78 a18/s5 79 a17/s4 80 a16/s3 81 s0 82 s1 83 s2 84 pereq (v ss ) 85 nmi 86 test 87 error (v cc ) 88 ready 89 v cc 90 v ss 91 ucs 92 lcs 93 p1.7/gcs7 94 p1.6/gcs6 95 p1.5/gcs5 96 p1.4/gcs4 97 p1.3/gcs3 98 p1.2/gcs2 99 p1.1/gcs1 100 p1.0/gcs0 19
80c186ec/188ec , 80l186ec/188ec 27243 4 C 4 note: thi s i s th e fp o numbe r locatio n (indicate d b y xs). figur e 5 : qua d fla t pac k (eiaj ) pinou t diagram 20 x
80c186ec/188ec, 80l186ec/188ec table 7. sqfp pin functions with location ad bus ad0 73 ad1 72 ad2 71 ad3 70 ad4 66 ad5 65 ad6 64 ad7 63 ad8 (a8) 60 ad9 (a9) 59 ad10 (a10) 58 ad11 (a11) 57 ad12 (a12) 56 ad13 (a13) 55 ad14 (a14) 54 ad15 (a15) 53 a16 77 a17 76 a18 75 a19/once 74 bus control ale 52 bhe (rfsh )51 s0 78 s1 79 s2 80 rd 50 wr 49 ready 85 dt/r 46 den 47 lock 48 hold 44 hlda 45 processor control resin 8 resout 7 clkin 10 oscout 11 clkout 6 test /busy 83 nmi 82 int0 30 int1 31 int2 32 int3 33 int4 40 int5 41 int6 42 int7 43 inta 34 pereq (v ss )81 error (v cc )84 ncs (n.c.) 35 pdtmr 9 power and ground v cc 13 v cc 14 v cc 38 v cc 62 v cc 67 v cc 69 v cc 86 v ss 12 v ss 15 v ss 37 v ss 39 v ss 61 v ss 68 v ss 87 i/o ucs 88 lcs 89 p1.0/gcs0 97 p1.1/gcs1 96 p1.2/gcs2 95 p1.3/gcs3 94 p1.4/gcs4 93 p1.5/gcs5 92 p1.6/gcs6 91 p1.7/gcs7 90 p2.0/rxd0 16 p2.1/txd0 17 p2.2/bclk0 18 p2.3/cts0 19 p2.4/rxd1 20 p2.5/txd1 21 p2.6/bclk1 22 p2.7/cts1 23 p3.0/rxi1 24 p3.1/txi1 25 p3.2/dmai0 26 p3.3/dmai1 27 p3.4 28 p3.5 29 drq0 98 drq1 99 drq2 100 drq3 1 t0in 3 t0out 2 t1in 5 t1out 4 wdtout 36 21
80c186ec/188ec, 80l186ec/188ec table 8. sqfp pin locations with pin names pin name 1 drq3 2 t0out 3 t0in 4 t1out 5 t1in 6 clkout 7 resout 8 resin 9 pdtmr 10 clkin 11 oscout 12 v ss 13 v cc 14 v cc 15 v ss 16 p2.0/rxd0 17 p2.1/txd0 18 p2.2/bclk0 19 p2.3/cts0 20 p2.4/rxd1 21 p2.5/txd1 22 p2.6/bclk1 23 p2.7/cts1 24 p3.0/rxi1 25 p3.1/txi1 pin name 26 p3.2/dmai0 27 p3.3/dmai1 28 p3.4 29 p3.5 30 int0 31 int1 32 int2 33 int3 34 inta 35 nsc (n.c.) 36 wdtout 37 v ss 38 v cc 39 v ss 40 int4 41 int5 42 int6 43 int7 44 hold 45 hlda 46 dt/r 47 den 48 lock 49 wr 50 rd pin name 51 bhe (rfsh ) 52 ale 53 ad15 (a15) 54 ad14 (a14) 55 ad13 (a13) 56 ad12 (a12) 57 ad11 (a11) 58 ad10 (a10) 59 ad9 (a9) 60 ad8 (a8) 61 v ss 62 v cc 63 ad7 (a7) 64 ad6 (a6) 65 ad5 66 ad4 67 v cc 68 v ss 69 v cc 70 ad3 71 ad2 72 ad1 73 ad0 74 a19/once 75 ad18 pin name 76 a17 77 a16 78 s0 79 s1 80 s2 81 pereq (v ss ) 82 mni 83 test /busy (test ) 84 error (v cc ) 85 ready 86 v cc 87 v ss 88 ucs 89 lcs 90 p1.7/gcs7 91 p1.6/gs6 92 p1.5/gcs5 93 p1.4/gcs4 94 p1.3/gcs3 95 p1.2/gcs2 96 p1.1/gcs1 97 p1.0/gcs0 98 drq0 99 drq1 100 drq2 22
80c186ec/188ec , 80l186ec/188ec 27243 4 C 5 note: thi s i s th e fp o numbe r locatio n (indicate d b y xs) figur e 6 : 100-pi n shrin k qua d fla t pac k packag e (sqfp) 23 x
80c186ec/188ec, 80l186ec/188ec package thermal specifications the 80c186ec/80l186ec is specified for operation when t c (the case temperature) is within the range of b 40 cto a 100 c. t c may be measured in any environment to determine whether the processor is within the specified operating range. the case tem- perature must be measured at the center of the top surface. t a (the ambient temperature) can be calculated from i ca (thermal resistance from the case to ambi- ent) with the following equation: t a e t c b p * i ca typical values for i ca at various airflows are given in table 9. p (the maximum power consumptione specified in watts) is calculated by using the maxi- mum i cc and v cc of 5.5v. table 9. thermal resistance ( i ca ) at various airflows (in c/watt) airflow in ft/min (m/sec) 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.04) (4.06) (5.07) i ca (pqfp) 27.0 22.0 18.0 15.0 14.0 13.5 i ca (qfp) 64.5 55.5 51.0 tbd tbd tbd i ca (sqfp) 62.0 tbd tbd tbd tbd tbd 24
80c186ec/188ec, 80l186ec/188ec electrical specifications absolute maximum ratings storage temperature b 65 cto a 150 c case temperature under bias b 65 cto a 100 c supply voltage with respect to v ss b 0.5v to a 6.5v voltage on other pins with respect to v ss b 0.5v to v cc a 0.5v notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. recommended connections power and ground connections must be made to multiple v cc and v ss pins. every 80c186ec-based circuit board should include separate power (v cc ) and ground (v ss ) planes. every v cc pin must be connected to the power plane, and every v ss pin must be connected to the ground plane. liberal de- coupling capacitance should be placed near the processor. the processor can cause transient pow- er surges when its output buffers transition, particu- larly when connected to large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. inductance is reduced by placing the de- coupling capacitors as close as possible to the proc- essor v cc and v ss package pins. always connect any unused input to an appropriate signal level. in particular, unused interrupt inputs (nmi, int0:7) should be connected to v ss through a pull-down resistor. leave any unused output pin un- connected. 25
80c186ec/188ec, 80l186ec/188ec dc specifications (80c186ec/80c188ec) symbol parameter min max units notes v cc supply voltage 4.5 5.5 v v il input low voltage b 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 2 ma (min) v hyr input hysteresis on resin 0.5 v i li input leakage current for pins: g 15 m a0 s v in s v cc ad15:0 (ad7:0, a15:8), ready, hold, resin , clkin, test /busy, nmi, int7:0, t0in, t1in, p2.7 p2.0, p3.5 p3.0, drq3:0, pereq, error i liu input leakage for pins with pullups b 0.275 b 5mav in e 0.7 v cc active during reset: (note 1) a19:16, lock i lo output leakage for floated output g 15 m a 0.45 s v out s v cc pins (note 2) i cc supply current cold (in reset) 80c186ec25 125 ma (notes 3, 7) 80c186ec20 100 ma (note 3) 80c186ec13 70 ma (note 3) i id supply current in idle mode 80c186ec25 92 ma (notes 4, 7) 80c186ec20 76 ma (note 4) 80c186ec13 50 ma (note 4) i pd supply current in powerdown mode 80c186ec25 100 m a (notes 5, 7) 80c186ec20 100 m a (note 5) 80c186ec13 100 m a (note 5) c in input pin capacitance 0 15 pf t f e 1 mhz c out output pin capacitance 0 15 pf t f e 1 mhz (note 6) notes: 1. these pins have an internal pull-up device that is active while resin is low and once mode is not active. sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. tested by outputs being floated by invoking once mode or by asserting hold. 3. measured with the device in reset and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 4. measured with the device in halt (idle mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 5. measured with the device in halt (powerdown mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 6. output capacitance is the capacitive load of a floating output pin. 7. operating conditions for 25 mhz is 0 cto a 70 c, v cc e 5.0 g 10%. 26
80c186ec/188ec, 80l186ec/188ec dc specifications (80l186ec13/80l188ec13) symbol parameter min max units notes v cc supply voltage 2.7 5.5 v v il input low voltage b 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 2 ma (min) v hyr input hysteresis on resin 0.5 v i li input leakage current for pins: g 15 m a0 s v in s v cc ad15:0 (ad7:0, a15:8), ready, hold, resin , clkin, test /busy, nmi, int7:0, t0in, t1in, p2.7 p2.0, p3.5 p3.0, drq3:0, pereq, error i liu input leakage for pins with pullups b 0.275 b 5mav in e 0.7 v cc active during reset: (note 1) a19:16, lock i lo output leakage for floated output g 15 m a 0.45 s v out s v cc pins (note 2) i cc supply current cold (in reset) (note 3) 80l186ec-13 36 ma i id supply current in idle mode (note 4) 80l186ec-13 24 ma i pd supply current in powerdown mode (note 5) 80l186ec-13 30 m a c in input pin capacitance 0 15 pf t f e 1 mhz c out output pin capacitance 0 15 pf t f e 1 mhz (note 6) notes: 1. these pins have an internal pull-up device that is active while resin is low and once mode is not active. sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. tested by outputs being floated by invoking once mode or by asserting hold. 3. measured with the device in reset and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 4. measured with the device in halt (idle mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 5. measured with the device in halt (powerdown mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 6. output capacitance is the capacitive load of a floating output pin. 27
80c186ec/188ec, 80l186ec/188ec dc specifications (80l186ec16/80l188ec16) (operating temperature 0 cto70 c) symbol parameter min max units notes v cc supply voltage 3.0 5.5 v v il input low voltage b 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3 ma (min) v oh output high voltage v cc b 0.5 v i oh eb 2 ma (min) v hyr input hysteresis on resin 0.5 v i li input leakage current for pins: g 15 m a0 s v in s v cc ad15:0 (ad7:0, a15:8), ready, hold, resin , clkin, test /busy, nmi, int7:0, t0in, t1in, p2.7 p2.0, p3.5 p3.0, drq3:0, pereq, error i liu input leakage for pins with pullups b 0.275 b 5mav in e 0.7 v cc active during reset: (note 1) a19:16, lock i lo output leakage for floated output g 15 m a 0.45 s v out s v cc pins (note 2) i cc supply current cold (in reset) (note 3) 80l186ec-16 45 ma i id supply current in idle mode (note 4) 80l186ec-16 35 ma i pd supply current in powerdown mode (note 5) 80l186ec-16 50 m a c in input pin capacitance 0 15 pf t f e 1 mhz c out output pin capacitance 0 15 pf t f e 1 mhz (note 6) notes: 1. these pins have an internal pull-up device that is active while resin is low and once mode is not active. sourcing more current than specified (on any of these pins) may invoke a factory test mode. 2. tested by outputs being floated by invoking once mode or by asserting hold. 3. measured with the device in reset and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 4. measured with the device in halt (idle mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 5. measured with the device in halt (powerdown mode active) and at worst case frequency, v cc , and temperature with all outputs loaded as specified in ac test conditions, and all floating outputs driven to v cc or gnd. 6. output capacitance is the capacitive load of a floating output pin. 28
80c186ec/188ec, 80l186ec/188ec i cc versus frequency and voltage the i cc consumed by the processor is composed of two components: 1. i pd ethe quiescent current that represents inter- nal device leakage. measured with all inputs at either v cc or ground and no clock applied. 2. i ccs ethe switching current used to charge and discharge internal parasitic capacitance when changing logic levels. i ccs is related to both the frequency of operation and the device supply voltage (v cc ). i ccs is given by the formula: power e v * i e v 2 * c dev * f . . . i ccs e v * c dev * f where: v e supply voltage (v cc ) c dev e device capacitance f e operating frequency measuring c pd on a device like the 80c186ec would be difficult. instead, c pd is calculated using the above formula with i cc values measured at known v cc and frequency. using the c pd value, the user can calculate i cc at any voltage and frequency within the specified operating range. example. calculate typical i cc at 14 mhz, 5.2v v cc . i cc e i pd a i ccs e 0.1 ma a 5.2v * 0.77 * 14 mhz e 56.2 ma pdtmr pin delay calculation the pdtmr pin provides a delay between the as- sertion of nmi and the enabling of the internal clocks when exiting powerdown mode. a delay is required only when using the on chip oscillator to allow the crystal or resonator circuit to stabilize. note: the pdtmr pin function does not apply when resin is asserted (i.e. a device reset while in pow- erdown is similar to a cold reset and resin must remain active until after the oscillator has stabilized. to calculate the value of capacitor to use to provide a desired delay, use the equation: 440 c t e c pd (5v, 25 c) where: t e desired delay in seconds c pd e capacitive load on pdtmr in microfarads example. for a delay of 300 m s, a capacitor value of c pd e 440 c (300 c 10 b 6 e 0.132 m f is required. round up to a standard (available) capacitor value. note: the above equation applies to delay time longer than 10 m s and will compute the typical capaci- tance needed to achieve the desired delay. a delay variance of a 50% to b 25% can occur due to temperature, voltage, and device process ex- tremes. in general, higher v cc and/or lower tem- peratures will decrease delay time, while lower v cc and/or higher temperature will increase delay time. parameter typical max units notes cpd 0.77 1.37 ma/v * mhz 1, 2 cpd (idle mode) 0.55 0.96 ma/v * mhz 1, 2 notes: 1. maximum c pd is measured at b 40 c with all outputs loaded as specified in the ac test conditions and the device in reset (or idle mode). due to tester limitations, clkout and oscout also have 50 pf loads that increase i cc by v * c * f. 2. typical c pd is calculated at 25 c assuming no loads on clkout or oscout and the device in reset (or idle mode). 29
80c186ec/188ec, 80l186ec/188ec ac specifications ac characteristicse80c186ec25 symbol parameter 25 mhz units notes min max input clock t f clkin frequency 0 50 mhz 1 t c clkin period 20 % ns 1 t ch clkin high time 8 % ns 1, 2 t cl clkin low time 8 % ns 1, 2 t cr clkin rise time 1 10 ns 1, 3 t cf clkin fall time 1 10 ns 1, 3 output clock t cd clkin to clkout delay 0 17 ns 1, 4 t clkout period 2 * t c ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1 6 ns 1, 5 t pf clkout fall time 1 6 ns 1, 5 output delays t chov1 ale, s2:0 , den , dt/r , 3 17 ns 1, 4, 6, 7 bhe (rfsh ), lock , a19:16 t chov2 gcs0:7 , lcs , ucs , ncs ,rd ,wr 3 20 ns 1,4,6,8 t clov1 bhe (rfsh ), den , lock , resout, 3 17 ns 1, 4, 6 hlda, t0out, t1out, a19:16 t clov2 rd ,wr , gcs7:0 , lcs , ucs , ad15:0 3 20 ns 1, 4, 6 (ad7:0, a15:8), ncs , inta1:0 , s2:0 t chof rd ,wr , bhe (rfsh ), dt/r , 0 20 ns 1 lock , s2:0 , a19:16 t clof den , ad15:0 (ad7:0, a15:8) 0 20 ns 1 30
80c186ec/188ec, 80l186ec/188ec ac specifications ac characteristicse80c186ec25 (continued) symbol parameter 25 mhz units notes min max synchronous inputs t chis test , nmi, int4:0, bclk1:0, t1:0in, ready, cts1:0 ,10 ns1,9 p2.6, p2.7 t chih test , nmi, int4:0, bclk1:0, t1:0in, ready, cts1:0 3ns1,9 t clis ad15:0 (ad7:0), ready 10 ns 1, 10 t clih ready, ad15:0 (ad7:0) 3 ns 1, 10 t clis hold, pereq, error 10 ns 1, 9 t clih hold, pereq, error 3ns1,9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 13 for capacitive derating information. 5. specified for a 50 pf load, see figure 14 for rise and fall times outside 50 pf. 6. see figure 14 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 31
80c186ec/188ec, 80l186ec/188ec ac specifications ac characteristicse80c186ec-20/80c186ec-13 symbol parameter min max min max unit notes input clock 20 mhz 13 mhz tf clkin frequency 0 40 0 26 mhz 1 tc clkin period 25 % 38.5 % ns 1 tch clkin high time 10 % 12 % ns 1, 2 tcl clkin low time 10 % 12 % ns 1, 2 tcr clkin rise time 1 10 1 10 ns 1, 3 tcf clkin fall time 1 10 1 10 ns 1, 3 output clock t cd clkin to clkout delay 0 17 0 23 ns 1, 4 t clkout period 2 * tc 2 * tc ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5 (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5 (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1616ns1,5 t pf clkout fall time 1616ns1,5 output delays t chov1 ale, s2:0 , den , dt/r , 3 20 3 25 ns 1,4,6,7 bhe (rfsh ), lock , a19:16 t chov2 gcs7:0 , lcs , ucs , 3 23 3 30 ns 1,4,6,8 rd ,wr , ncs , wdtout t clov1 bhe (rfsh ), den , lock , resout, 3 20 3 25 ns 1, 4, 6 hlda, t0out, t1out t clov2 rd ,wr , gsc7:0 , lcs , ucs , ad15:0 3 23 3 30 ns 1, 4, 6 (ad7:0, a15:8), ncs , inta , s2:0 , a19:16 t chof rd ,wr , bhe (rfsh ), dt/r , lock , 025030ns1 s2:0 , a19:16 t clof den , ad15:0 (ad7:0, a15:8) 0 25 0 30 ns 1 input requirements t chis test , nmi, t1in, t0in, ready, 10 10 ns 1, 9 cts1:0 , bclk1:0, p3.4, p3.5 t chih test , nmi, t1in, t0in, ready, 3 3 ns 1, 9 cts1:0 , bclk1:0, p3.4, p3.5 t clis ad15:0 (ad7:0), ready 10 10 ns 1, 10 t clih ad15:0 (ad7:0), ready 3 3 ns 1, 10 t clis hold, resin , pereq, error , drq3:0 10 10 ns 1, 9 t clih hold, resin , rereq, error , drq3:0 3 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 14 for capacitive derating information. 5. specified for a 50 pf load, see figure 15 for rise and fall times outside 50 pf. 6. see figure 15 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. 32
80c186ec/188ec, 80l186ec/188ec ac characteristicse80l186ec13 symbol parameter min max unit notes input clock 13 mhz t f clkin frequency 0 26 mhz 1 t c clkin period 38.5 % ns 1 t ch clkin high time 15 % ns 1, 2 t cl clkin low time 15 % ns 1, 2 t cr clkin rise time 1 10 ns 1, 3 t cf clkin fall time 1 10 ns 1, 3 output clock t cd clkin to clkout delay 0 20 ns 1, 4 t clkout period 2 * tc ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1 10 ns 1, 5 t pf clkout fall time 1 10 ns 1, 5 output delays t chov1 s2:0 , dt/r , bhe , lock 3 28 ns 1,4,6,7 t chov2 lcs , ucs , den , a19:16, rd ,wr , ncs , 3 32 ns 1, 4, 6, 8 wdtout , ale t chov3 gcs7:0 3 34 ns 1,4,6 t clov1 lock , resout, hlda, t0out, t1out 3 28 ns 1, 4, 6 t clov2 rd ,wr , ad15:0 (ad7:0, a15:8), bhe 3 32 ns 1,4,6 (rfsh ), ncs , inta , den t clov3 gsc7:0 , lcs , ucs 3 34 ns 1,4,6 t clov4 s2:0 , a19:16 3 37 ns 1, 4, 6 t chof rd ,wr , bhe (rfsh ), dt/r , lock , 0 30 ns 1 s2:0 , a19:16 t clof den , ad15:0 (ad7:0, a15:8) 0 35 ns 1 input requirements t chis test , nmi, t1in, t0in, ready, 20 ns 1, 9 cts1:0 , bclk1:0, p3.4, p3.5 t chih test , nmi, t1in, t0in, ready, 3 ns 1, 9 cts1:0 , bclk1:0, p3.4, p3.5 t clis ad15:0 (ad7:0), ready 20 ns 1, 10 t clih ad15:0 (ad7:0), ready 3 ns 1, 10 t clis hold, resin , pereq, error , drq3:0 20 ns 1, 9 t clih hold, resin , rereq, error , drq3:0 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 14 for capacitive derating information. 5. specified for a 50 pf load, see figure 15 for rise and fall times outside 50 pf. 33
80c186ec/188ec, 80l186ec/188ec ac characteristicse80l186ec13 (continued) notes: 6. see figure 15 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. ac characteristicse80l186ec16 (operating temperature 0 cto70 c) symbol parameter min max unit notes input clock 16 mhz t f clkin frequency 0 32 mhz 1 t c clkin period 31.25 % ns 1 t ch clkin high time 13 % ns 1, 2 t cl clkin low time 13 % ns 1, 2 t cr clkin rise time 1 10 ns 1, 3 t cf clkin fall time 1 10 ns 1, 3 output clock t cd clkin to clkout delay 0 20 ns 1, 4 t clkout period 2 * tc ns 1 t ph clkout high time (t/2) b 5 (t/2) a 5ns 1 t pl clkout low time (t/2) b 5 (t/2) a 5ns 1 t pr clkout rise time 1 9 ns 1, 5 t pf clkout fall time 1 9 ns 1, 5 output delays t chov1 s2:0 , dt/r , bhe , lock 3 25 ns 1,4,6,7 t chov2 lcs , ucs , den , a19:16, rd ,wr , ncs , 3 30 ns 1, 4, 6, 8 wdtout , ale t chov3 gcs7:0 3 32 ns 1,4,6 t clov1 lock , resout, hlda, t0out, t1out 3 25 ns 1, 4, 6 t clov2 rd ,wr , ad15:0 (ad7:0, a15:8), bhe 3 30 ns 1,4,6 (rfsh ), ncs , inta , den t clov3 gsc7:0 , lcs , ucs 3 32 ns 1,4,6 t clov4 s2:0 , a19:16 3 34 ns 1, 4, 6 t chof rd ,wr , bhe (rfsh ), dt/r , lock , 0 28 ns 1 s2:0 , a19:16 t clof den , ad15:0 (ad7:0, a15:8) 0 32 ns 1 input requirements t chis test , nmi, t1in, t0in, ready, 15 ns 1, 9 cts1:0 , bclk1:0, p3.4, p3.5 t chih test , nmi, t1in, t0in, ready, 3 ns 1, 9 cts1:0 , bclk1:0, p3.4, p3.5 t clis ad15:0 (ad7:0), ready 15 ns 1, 10 t clih ad15:0 (ad7:0), ready 3 ns 1, 10 t clis hold, resin , pereq, error , drq3:0 15 ns 1, 9 t clih hold, resin , pereq, error , drq3:0 3 ns 1, 9 34
80c186ec/188ec, 80l186ec/188ec ac characteristicse80l186ec16 (continued) notes: 1. see ac timing waveforms , for waveforms and definition. 2. measure at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 14 for capacitive derating information. 5. specified for a 50 pf load, see figure 15 for rise and fall times outside 50 pf. 6. see figure 15 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10. setup and hold are required for proper operation. relative timings (80c186ec-25/20/13, 80l186ec-16/13) symbol parameter min max unit notes relative timings t lhll ale active pulse width t b 15 ns t avll ad valid setup before ale falls (/2 t b 10 ns t plll chip select valid before ale falls (/2 t b 10 ns 1 t llax ad hold after ale falls (/2 t b 10 ns t llwl ale falling to wr falling (/2 t b 15 ns 1 t llrl ale falling to rd falling (/2 t b 15 ns 1 t whlh wr rising to next ale rising (/2 t b 10 ns 1 t afrl ad float to rd falling 0 ns t rlrh rd active pulse width 2t b 5ns2 t wlwh wr active pulse width 2t b 5ns2 t rhax rd rising to next address active t b 15 ns t whdx output data hold after wr rising t b 15 ns t whph wr rise to chip select rise (/2 t b 10 ns 1 t rhph rd rise to chip select rise (/2 t b 10 ns 1 t phpl chip select inactive to next chip (/2 t b 10 ns 1 select active t ovrh once active setup to resin rising t ns t rhox once hold after resin rise t ns t ihil inta high to next inta low 4t b 5ns4 during inta cycle t ilih inta active pulse width 2t b 5ns2,4 t cvil cas2:0 setup before 2nd inta 8t ns 2, 4 pulse low t ilcx cas2:0 hold after 2nd inta pulse low 4t ns 2, 4 t ires interrupt resolution time 150 ns 3 t irlh ir low time to reset edge detector 50 ns t irhif ir hold time after 1st inta falling 25 ns 4, 5 35
80c186ec/188ec, 80l186ec/188ec relative timings (80c186ec-25/20/13, 80l186ec-16/13) notes: 1. assumes equal loading on both pins. 2. can be extended using wait states. 3. interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the 8259a module going active. this is not directly measureable by the user. for interrupt pin int7 the delay from an active signal to an active input to the cpu would actually be twice the t ires value since the signal must pass through two 8259a modules. 4. see inta cycle waveforms for definition. 5. to guarantee interrupt is not spurious. serial port mode 0 timings (80c186ec-25/20/13, 80l186ec-16/13) symbol parameter min max unit notes relative timings t xlxl txd clock period t (n a 1) ns 1, 2 t xlxh txd clock low to clock high (n l 1) 2t b 35 2t a 35 ns 1 t xlxh txd clock low to clock high (n e 1) t b 35 t a 35 ns 1 t xhxl txd clock high to clock low (n l 1) (n b 1) t b 35 (n b 1) t a 35 ns 1, 2 t xhxl txd clock high to clock low (n e 1) t b 35 t a 35 ns 1 t qvxh rxd output data setup to txd (n b 1)t b 35 ns 1, 2 clock high (n l 1) t qvxh rxd output data setup to txd t b 35 ns 1 clock high (n e 1) t xhqx rxd output data hold after txd 2t b 35 ns 1 clock high (n l 1) t xhqx rxd output data hold after txd t b 35 ns 1 clock high (n e 1) t xhqz rxd output data float after last t a 20 ns 1 txd clock high t dvxh rxd input data setup to txd t a 20 ns 1 clock high t xhdx rxd input data setup after txd 0 ns 1 clock high notes: 1. see figure 13 for waveforms. 2. n is the value in the bxcmp register ignoring the iclk bit. 36
80c186ec/188ec, 80l186ec/188ec ac test conditions the ac specifications are tested with the 50 pf load shown in figure 7. see the derating curves section to see how timings vary with load capacitance. specifications are measured at the v cc /2 crossing point, unless otherwise specified. see ac timing waveforms for ac specification definitions, test pins and illustrations. 272434 6 c l e 50 pf for all signals figure 7. ac test load ac timing waveforms 272434 7 figure 8. input and output clock waveforms 37
80c186ec/188ec, 80l186ec/188ec 272434 8 figure 9. output delay and float waveforms 272434 9 figure 10. input setup and hold 272434 10 figure 11. relative interrupt signal timings 38
80c186ec/188ec, 80l186ec/188ec 272434 11 figure 12. relative signal waveform 272434 12 figure 13. serial port mode 0 waveform 39
80c186ec/188ec, 80l186ec/188ec derating curves 272434 13 figure 14. typical output delay variations versus load capacitance 272434 14 figure 15. typical rise and fall variations versus load capacitance reset the processor will perform a reset operation any time the resin pin is active. the resin pin is syn- chronized before it is presented internally, which means that the clock must be operating before a reset can take effect. from a power-on state, resin must be held active (low) in order to guarantee cor- rect initialization of the processor. failure to pro- vide resin while the device is powering up will result in unspecified operation of the device. figure 16 shows the correct reset sequence when first applying power to the processor. an external clock connected to clkin must not exceed the v cc threshold being applied to the processor. this is nor- mally not a problem if the clock driver is supplied with the same v cc that supplies the processor. when attaching a crystal to the device, resin must remain active until both v cc and clkout are stable (the length of time is application specific and de- pends on the startup characteristics of the crystal circuit). the resin pin is designed to operate cor- rectly using a rc reset circuit, but the designer must ensure that the ramp time for v cc is not so long that resin is never sampled at a logic low level when v cc reaches minimum operating conditions. figure 17 shows the timing sequence when resin is applied after v cc is stable and the device has been operating. note that a reset will terminate all activity and return the processor to a known operat- ing state. any bus operation that is in progress at the time resin is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating). while resin is active, bus signals lock , a19/s16/once and a18:16 are configured as in- puts and weakly held high by internal pullup transis- tors. only a19/once can be overdriven to a low and is used to enable the once mode. forcing lock or a18:16 low at any time while resin is low is prohibited and will cause unspecified device oper- ation. 40
80c186ec/188ec, 80l186ec/188ec figure 16. cold reset waveforms 272434 15 note: clkout synchronization occurs on the rising edge of resin . if resin is sampled high while clkout is high (solid line), then clkout will remain low for two clkin periods. if resin is sampled high while clkout is low (dashed line), then clkout will not be affected. pin names in parentheses apply to 80c188ec/80l188ec. 41
80c186ec/188ec, 80l186ec/188ec figure 17. warm reset waveforms 272434 16 note: clkout synchronization occurs on the rising edge of resin . if resin is sampled high while clkout is high (solid line), then clkout will remain low for two clkin periods. if resin is sampled high while clkout is low (dashed line), then clkout will not be affected. pin names in parentheses apply to 80c188ec/80l188ec. 42
80c186ec/188ec, 80l186ec/188ec bus cycle waveforms figures 18 through 24 present the various bus cy- cles that are generated by the processor. what is shown in the figure is the relationship of the various bus signals to clkout. these figures along with the information present in ac specifications allow the user to determine all the critical timing analysis needed for a given application. 272434 17 pin names in parentheses apply to 80c188ec/80l188ec. figure 18. memory read, i/o read, instruction fetch and refresh waveforms 43
80c186ec/188ec, 80l186ec/188ec 272434 18 pin names in parentheses apply to 80c188ec/80l188ec. figure 19. memory write and i/o write cycle waveforms 44
80c186ec/188ec, 80l186ec/188ec 272434 19 notes: 1. address information is invalid. if previous bus cycle was a read, then the ad15:0 (ad7:0) lines will float during t1. otherwise, the ad15:0 (ad7:0) lines will continue to drive during t1 (data is invalid). all other control lines are in their inactive state. 2. all address lines drive zeros while in powerdown or idle mode. pin names in parentheses apply to 80c188ec/80l188ec. figure 20. halt cycle waveforms 45
80c186ec/188ec, 80l186ec/188ec 272434 20 pin names in parentheses apply to 80c188ec/80l188ec. figure 21. interrupt acknowledge cycle waveforms 46
80c186ec/188ec, 80l186ec/188ec 272434 21 pin names in parentheses apply to 80c188ec/80l188ec. figure 22. hold/hlda cycle waveforms 47
80c186ec/188ec, 80l186ec/188ec 272434 22 pin names in parentheses apply to 80c188ec/80l188ec. figure 23. refresh during hlda waveforms 48
80c186ec/188ec, 80l186ec/188ec 272434 23 notes: 1. ready must be low by either edge to cause a wait state. 2. lighter lines indicate read cycles, darker lines indicate write cycles. pin names in parentheses apply to 80c188ec/80l188ec. figure 24. ready cycle waveforms 49
80c186ec/188ec, 80l186ec/188ec 80c186ec/80c188ec execution timings a determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. the fol- lowing instruction timings represent the minimum execution time in clock cycles for each instruction. the timings given are based on the following as- sumptions: # the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # no wait states or bus holds occur. # all word-data is located on even-address bound- aries (80c186ec only). all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (biu) and exe- cution unit. with a 16-bit biu, the 80c186ec has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. therefore, actual program execu- tion time will not be substantially greater than that derived from adding the instruction timings shown. the 80c188ec 8-bit biu is limited in its performance relative to the execution unit. a sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown. 50
80c186ec/188ec, 80l186ec/188ec instruction set summary function format 80c186ec 80c188ec comments clock clock cycles cycles data transfer mov e move: register to register/memory 1000100w modreg r/m 2/12 2/12 * register/memory to register 1000101w modreg r/m 2/9 2/9 * immediate to register/memory 1100011w mod000 r/m data data if w e 1 12/13 12/13 8/16-bit immediate to register 1011w reg data data if w e 1 3/4 3/4 8/16-bit memory to accumulator 1010000w addr-low addr-high 8 8 * accumulator to memory 1010001w addr-low addr-high 9 9 * register/memory to segment register 10001110 mod0reg r/m 2/9 2/13 segment register to register/memory 10001100 mod0reg r/m 2/11 2/15 push e push: memory 11111111 mod110 r/m 16 20 register 01010 reg 10 14 segment register 000reg110 9 13 immediate 011010s0 data data if s e 01014 pusha e push all 01100000 36 68 pop e pop: memory 10001111 mod000 r/m 20 24 register 01011 reg 10 14 segment register 000reg111 (reg i 01) 8 12 popa e popall 01100001 51 83 xchg e exchange: register/memory with register 1000011w modreg r/m 4/17 4/17 * register with accumulator 10010 reg 3 3 in e input from: fixed port 1110010w port 10 10 * variable port 1110110w 8 8 * out e output to: fixed port 1110011w port 9 9 * variable port 1110111w 7 7 * xlat e translate byte to al 11010111 11 15 lea e load ea to register 10001101 modreg r/m 6 6 lds e load pointer to ds 11000101 modreg r/m (mod i 11) 18 26 les e load pointer to es 11000100 modreg r/m (mod i 11) 18 26 lahf e load ah with flags 10011111 2 2 sahf e store ah into flags 10011110 3 3 pushf e push flags 10011100 9 13 popf e pop flags 10011101 8 12 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. 51
80c186ec/188ec, 80l186ec/188ec instruction set summary (continued) function format 80c186ec 80c188ec comments clock clock cycles cycles data transfer (continued) segment e segment override: cs 00101110 2 2 ss 00110110 2 2 ds 00111110 2 2 es 00100110 2 2 arithmetic add e add: reg/memory with register to either 000000dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod000 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0000010w data data if w e 1 3/4 3/4 8/16-bit adc e add with carry: reg/memory with register to either 000100dw modreg r/m 3/10 3/10 * immediate to register/memory 100000sw mod010 r/m data data if s w e 01 4/16 4/16 * immediate to accumulator 0001010w data data if w e 1 3/4 3/4 8/16-bit inc e increment: register/memory 1111111w mod000 r/m 3/15 3/15 * register 01000 reg 3 3 sub e subtract: reg/memory and register to either 001010dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod101 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0010110w data data if w e 1 3/4 3/4 * 8/16-bit sbb e subtract with borrow: reg/memory and register to either 000110dw modreg r/m 3/10 3/10 * immediate from register/memory 100000sw mod011 r/m data data if s w e 01 4/16 4/16 * immediate from accumulator 0001110w data data if w e 1 3/4 3/4 * 8/16-bit dec e decrement register/memory 1111111w mod001 r/m 3/15 3/15 * register 01001 reg 3 3 cmp e compare: register/memory with register 0011101w modreg r/m 3/10 3/10 * register with register/memory 0011100w modreg r/m 3/10 3/10 * immediate with register/memory 100000sw mod111 r/m data data if s w e 01 3/10 3/10 * immediate with accumulator 0011110w data data if w e 1 3/4 3/4 8/16-bit neg e change sign register/memory 1111011w mod011 r/m 3/10 3/10 * aaa e ascii adjust for add 00110111 8 8 daa e decimal adjust for add 00100111 4 4 aas e ascii adjust for subtract 00111111 7 7 das e decimal adjust for subtract 00101111 4 4 mul e multiply (unsigned): 1111011w mod100 r/m register-byte 2628 2628 register-word 3537 3537 memory-byte 3234 3234 memory-word 4143 4143 * shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. 52
80c186ec/188ec, 80l186ec/188ec instruction set summary (continued) function format 80c186ec 80c188ec comments clock clock cycles cycles arithmetic (continued) imul e integer multiply (signed): 1111011w mod101 r/m register-byte 2528 2528 register-word 3437 3437 memory-byte 3134 3234 memory-word 4043 4043 * imul e integer immediate multiply 011010s1 modreg r/m data data if s e 0 2225/ 2225/ (signed) 2932 2932 div e divide (unsigned): 1111011w mod110 r/m register-byte 29 29 register-word 38 38 memory-byte 35 35 memory-word 44 44 * idiv e integer divide (signed): 1111011w mod111 r/m register-byte 4452 4452 register-word 5361 5361 memory-byte 5058 5058 memory-word 5967 5967 * aam e ascii adjust for multiply 11010100 00001010 19 19 aad e ascii adjust for divide 11010101 00001010 15 15 cbw e convert byte to word 10011000 2 2 cwd e convert word to double word 10011001 4 4 logic shift/rotate instructions: register/memory by 1 1101000w modtttr/m 2/15 2/15 register/memory by cl 1101001w modtttr/m 5 a n/17 a n5 a n/17 a n register/memory by count 1100000w modtttr/m count 5 a n/17 a n5 a n/17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shl/sal 101 shr 111 sar and e and: reg/memory and register to either 001000dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod100 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0010010w data data if w e 1 3/4 3/4 * 8/16-bit test e and function to flags, no result: register/memory and register 1000010w modreg r/m 3/10 3/10 immediate data and register/memory 1111011w mod000 r/m data data if w e 1 4/10 4/10 * immediate data and accumulator 1010100w data data if w e 1 3/4 3/4 8/16-bit or e or: reg/memory and register to either 000010dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod001 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0000110w data data if w e 1 3/4 3/4 * 8/16-bit shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. 53
80c186ec/188ec, 80l186ec/188ec instruction set summary (continued) function format 80c186ec 80c188ec comments clock clock cycles cycles logic (continued) xor e exclusive or: reg/memory and register to either 001100dw modreg r/m 3/10 3/10 * immediate to register/memory 1000000w mod110 r/m data data if w e 1 4/16 4/16 * immediate to accumulator 0011010w data data if w e 1 3/4 3/4 8/16-bit not e invert register/memory 1111011w mod010 r/m 3/10 3/10 * string manipulation movs e move byte/word 1010010w 14 14 * cmps e compare byte/word 1010011w 22 22 * scas e scan byte/word 1010111w 15 15 * lods e load byte/wd to al/ax 1010110w 12 12 * stos e store byte/wd from al/ax 1010101w 10 10 * ins e input byte/wd from dx port 0110110w 14 14 outs e output byte/wd to dx port 0110111w 14 14 repeated by count in cx (rep/repe/repz/repne/repnz) movs e move string 11110010 1010010w 8 a 8n 8 a 8n * cmps e compare string 1111001z 1010011w 5 a 22n 5 a 22n * scas e scan string 1111001z 1010111w 5 a 15n 5 a 15n * lods e load string 11110010 1010110w 6 a 11n 6 a 11n * stos e store string 11110010 1010101w 6 a 9n 6 a 9n * ins e input string 11110010 0110110w 8 a 8n 8 a 8n * outs e output string 11110010 0110111w 8 a 8n 8 a 8n * control transfer call e call: direct within segment 11101000 disp-low disp-high 15 19 register/memory 11111111 mod010 r/m 13/19 17/27 indirect within segment direct intersegment 10011010 segment offset 23 31 segment selector indirect intersegment 11111111 mod011 r/m (mod i 11) 38 54 jmp e unconditional jump: short/long 11101011 disp-low 14 14 direct within segment 11101001 disp-low disp-high 14 14 register/memory 11111111 mod100 r/m 11/17 11/21 indirect within segment direct intersegment 11101010 segment offset 14 14 segment selector indirect intersegment 11111111 mod101 r/m (mod i 11) 26 34 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. 54
80c186ec/188ec, 80l186ec/188ec instruction set summary (continued) function format 80c186ec 80c188ec comments clock clock cycles cycles control transfer (continued) ret e return from call: within segment 11000011 16 20 within seg adding immed to sp 11000010 data-low data-high 18 22 intersegment 11001011 22 30 intersegment adding immediate to sp 11001010 data-low data-high 25 33 je/jz e jump on equal/zero 01110100 disp 4/13 4/13 jmp not jl/jnge e jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/jmp jle/jng e jump on less or equal/not greater 01111110 disp 4/13 4/13 taken jb/jnae e jump on below/not above or equal 01110010 disp 4/13 4/13 jbe/jna e jump on below or equal/not above 01110110 disp 4/13 4/13 jp/jpe e jump on parity/parity even 01111010 disp 4/13 4/13 jo e jump on overflow 01110 000 disp 4/13 4/13 js e jump on sign 01111000 disp 4/13 4/13 jne/jnz e jump on not equal/not zero 01110101 disp 4/13 4/13 jnl/jge e jump on not less/greater or equal 01111101 disp 4/13 4/13 jnle/jg e jump on not less or equal/greater 01111111 disp 4/13 4/13 jnb/jae e jump on not below/above or equal 01110011 disp 4/13 4/13 jnbe/ja e jump on not below or equal/above 01110111 disp 4/13 4/13 jnp/jpo e jump on not par/par odd 01111011 disp 4/13 4/13 jno e jump on not overflow 01110001 disp 4/13 4/13 jns e jump on not sign 01111001 disp 4/13 4/13 jcxz e jump on cx zero 11100011 disp 5/15 5/15 loop e loop cx times 11100010 disp 6/16 6/16 loop not loopz/loope e loop while zero/equal 11100001 disp 6/16 6/16 taken/loop loopnz/loopne e loop while not zero/equal 11100000 disp 6/16 6/16 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 19 l e 1 25 29 l l 1 22 a 16(n b 1) 26 a 20(n b 1) leave e leave procedure 11001001 8 8 int e interrupt: type specified 11001101 type 47 47 type 3 11001100 45 45 if int. taken/ into e interrupt on overflow 11001110 48/4 48/4 if int. not taken iret e interrupt return 11001111 28 28 bound e detect value out of range 01100010 modreg r/m 3335 3335 shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. 55
80c186ec/188ec, 80l186ec/188ec instruction set summary (continued) 80c186ec 80c188ec function format clock clock comments cycles cycles processor control clc e clear carry 11111000 2 2 cmc e complement carry 11110101 2 2 stc e set carry 11111001 2 2 cld e clear direction 11111100 2 2 std e set direction 11111101 2 2 cli e clear interrupt 11111010 2 2 sti e set interrupt 11111011 2 2 hlt e halt 11110100 2 2 wait e wait 10011011 6 6 if test e 0 lock e bus lock prefix 11110000 2 2 nop e no operation 10010000 3 3 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in 8086/8088 microsystems. note: * clock cycles shown for byte transfers, for word operations, add 4 clock cycles for all memory transfers. the effective address (ea) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a reg field if mod e 00 then disp e 0 * , disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-extended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high: disp-low if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp * if r/m e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) * except if mod e 00 and r/m e 110 then ea e disp-high: disp-low. ea calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table: 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register. the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment, which may not be overridden. 56
80c186ec/188ec, 80l186ec/188ec errata an 80c186ec/80l186ec with a stepid value of 0002h has no known errata. a device with a stepid of 0002h can be visually identified by noting the presence of an ``a'' or ``b'' alpha character next to the fpo number or the absence of any alpha char- acter. the fpo number location is shown in figures 4, 5 and 6. revision history this data sheet replaces the following data sheets: 272072-003 80c186ec 272076-003 80c188ec 272332-001 80l186ec 272333-001 80l188ec 272373-001 sb80c188ec/sb80l188ec 272372-001 sb80c186ec/sb80l186ec 57

▲Up To Search▲

Price & Availability of QU80C186EC25

	To Download QU80C186EC25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .